Stable high mobility motft and fabrication at low temperature

ABSTRACT

A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm 2 /Vs and a carrier concentration in a range of approximately 10 18  cm −3  to approximately 5×10 19  cm −3 . Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of currently pending U.S.application Ser. No. 13/902,514, filed 24 May 2013.

FIELD OF THE INVENTION

This invention generally relates to stable MOTFTs with high mobility anda process of fabrication at low temperature.

BACKGROUND OF THE INVENTION

There is presently a strong interest in metal oxide thin filmtransistors (MOTFT) because of the relatively high mobility innanocrystalline or amorphous states. Also, in many applications, it isdesirable to fabricate high mobility TFTs below certain temperatures sothat flexible and/or organic substrates can be used. The activesemiconductor layer in such TFTs must be formed/deposited at relativelylow temperatures (e.g. room temperature) but which still has relativelyhigh mobility and stability.

Poly-Si cannot be used for such active layer: the high mobility inpoly-Si TFTs is achieved by an increase in the grain size to a levelcomparable to the channel length. Only a small number of grains exist inthe channel region which leads to non-uniformity of devices because ofits large statistical fluctuation. Moreover, the high mobility inpoly-Si TFTs can only be achieved at relatively high temperature(typically, beyond 500° C.). A similar trend also existed in CdSe basedTFTs, in which high mobility is achieved when the active layer is formed(or post baked) over a certain temperature and when grain size becomessubstantial compared to the channel length. Similarly, thecharacteristics of TFTs with microcrystalline semiconductor can vary,even between adjacent devices in an array, due to the fluctuation ofgrain boundaries and the size and number of crystalline grains at eachTFT channel location. For example, in a conduction area under asub-micron gate, each different TFT can include from one or twopoly-silicon crystalline grains to several crystalline grains and thedifferent number of crystals in the conduction area will producedifferent characteristics. The dimensions and their physicalcharacteristics among different grains are also different.

It is known in the art that the channel length of presently standardthin film transistors is less than approximately 5 microns, especiallyfor portable display applications. For purposes of this disclosure theterm “amorphous” is defined as a material with grain size, along thechannel length, much less than the channel length of presently standardthin film transistors, e.g. approximately 100 nanometers or less. Insuch a way, the number of grains in a channel area of 5×5=25 μm² is morethan 10³, and the performance variation among different TFTs becomesnegligible in practical applications. Thus, a MOTFT with a channel layerformed of amorphous or nanocrystalline metal oxide insures uniformitysimilar to a-Si TFT by having a very large number of grain boundarieswhich results in much smaller performance fluctuations between devices.

A typical MOTFT based on amorphous In—Ga—Zn—O has a mobility less than15 cm²/Vs. However, a high quality Poly-Si TFT has a mobility around 40to 100 cm²/Vs. Many display applications call for mobility and stabilityas good as those demonstrated by poly-Si TFTs. It would, therefore, makea MOTFT even more attractive to improve the mobility beyond 40 cm²/Vs.In a MOTFT the mobility strongly depends on the volume carrierconcentration of the channel layer. To achieve high mobility, the volumecarrier concentration has to be equal to or greater than 10¹⁸/cm³. Butthere is a constraint on how high the volume carrier concentration canbe raised. In most applications, it is desirable to have a thresholdvoltage (V_(th)) close to zero and with a gate voltage in a rangesmaller than 20V. For instance, a TFT pixel driver for organic lightemitting diodes (OLED) or inorganic LEDs typically operate in a desiredrange of 0-10V and in a 0-15V range for AMLCDs.

The charge under control by the gate voltage is C_(g)(V_(g)−V_(th)),where C_(g) is the gate capacitance, V_(g) is the gate voltage, andV_(th) is the threshold voltage. So the volume carrier concentration isconstrained by C_(g)(V_(g)−V_(th))/d, where d is the thickness of thecarrier transport layer (MOTFT channel). To achieve a high mobilitydevice, the thickness ‘d’ of the carrier transport layer should be madeas small as possible. But the thickness d is constrained by the surfacequality (such as roughness and uniformity) of the underlying substrate.Typical surface roughness under the channel layer is around 0.2-2 nm forthe cases of dielectric layers on glass or polymer based substrates.

There are also other factors that must be considered in the case ofusing thin film carrier transport layers. For example, when the carriertransport layer is very thin, the stability may be or is easilycompromised by the environment. First, during processing, the very thinactive layer can be attacked and damaged or even destroyed by variousprocessing materials. Second, even if one managed to avoid the issuesprevalent in processing, the operating stability may be compromised ifthe very thin active layer is exposed to oxygen or water during devicefabrication and operation.

It would be highly advantageous, therefore, to remedy the foregoing andother deficiencies inherent in the prior art.

Accordingly, it is an object of the present invention to provide a newand improved process for fabricating a stable high mobility metal oxidethin film transistor (MOTFT).

It is another object of the present invention to provide a new andimproved process for fabricating a stable amorphous metal oxide thinfilm transistor (MOTFT) at low temperatures.

It is another object of the present invention to provide a new andimproved process for fabricating a stable amorphous metal oxide thinfilm transistor (MOTFT) with a mobility at or above 40 cm²/Vs.

It is another object of the present invention to provide a new andimproved stable amorphous high mobility metal oxide thin film transistor(MOTFT).

SUMMARY OF THE INVENTION

The desired objects of the instant invention are achieved in accordancewith a method of fabricating a stable high mobility amorphous MOTFTincluding the steps of providing a substrate with a gate formed thereonand a gate dielectric layer positioned over the gate. The method furtherincludes the steps of depositing a carrier transport structure on thegate dielectric layer. The carrier transport structure includes a layerof amorphous high mobility metal oxide adjacent the gate dielectric anda protective layer of material relatively inert compared to the layer ofmetal oxide, and depositing source/drain contacts on the protectivelayer.

The desired objects of the instant invention are achieved in accordancewith a specific method of fabricating a stable high mobility amorphousMOTFT including steps of providing a substrate with a gate formedthereon and a gate dielectric layer positioned over the gate. The methodfurther includes a carrier transport structure deposited by sputteringon the gate dielectric layer. The carrier transport structure includes alayer of amorphous high mobility metal oxide adjacent the gatedielectric and a relatively inert protective layer of material depositedon the layer of amorphous high mobility metal oxide both depositedwithout oxygen and in situ. The layer of amorphous metal oxide has amobility above 40 cm²/Vs and a carrier concentration in a range ofapproximately 10¹⁸ cm⁻³ to approximately 5×10¹⁹ cm⁻³. Source/draincontacts are positioned on the protective layer and in electricalcontact therewith.

The desired objects of the instant invention are also achieved inaccordance with a specific embodiment of a stable high mobilityamorphous MOTFT including a substrate with a gate formed thereon and agate dielectric layer positioned over the gate. A carrier transportstructure is sputtered on the gate dielectric layer. The carriertransport structure includes a layer of amorphous high mobility metaloxide adjacent the gate dielectric with a thickness in a range of equalto or less than approximately 5 nm and preferably approximately 2 nm, aprotective layer of relatively inert material deposited on the layer ofamorphous high mobility metal oxide with a thickness in a range of equalto or less than approximately 50 nm, and the layer of amorphous metaloxide having a mobility above 40 cm²/Vs and a carrier concentration in arange of approximately 10¹⁸ cm⁻³ to approximately 5×10¹⁹ cm⁻³.Source/drain contacts are positioned on and in electrical contact withthe protective layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and further and more specific objects and advantages ofthe instant invention will become readily apparent to those skilled inthe art from the following detailed description of a preferredembodiment thereof taken in conjunction with the drawings, in which:

FIG. 1 shows a simplified layer diagram illustrating several steps in aprocess of fabricating a high mobility stable amorphous metal oxidetransport layer for use in a high mobility metal oxide thin filmtransistor (MOTFT), in accordance with the present invention;

FIG. 2 illustrates an example of a stable high mobility metal oxide thinfilm transistor (defined as an “etch-stop” MOTFT) incorporating the highmobility stable transport layer of FIG. 1, in accordance with thepresent invention;

FIG. 3 illustrates an example of another stable high mobility metaloxide thin film transistor (defined as a “back-channel etch” MOTFT)incorporating the high mobility stable transport layer of FIG. 1, andthe source/drain contacts positioned on and in electrical contact withthe protective layer in accordance with the present invention;

FIG. 4A illustrates graphically Id-Vgs and mobility-Vgs data sets from aMOTFT with etch-stop structure described in FIG. 2;

FIG. 4B illustrates graphically Id-Vgs and mobility-Vgs data sets from aMOTFT with back-channel-etching structure illustrated in FIG. 3; and

FIG. 5 illustrates graphs of Id-Vgs and mobility-Vgs curves from a MOTFTmade in accordance with the present invention on a flexible PETsubstrate.

DETAILED DESCRIPTION OF THE DRAWINGS

Mobility in metal oxide semiconductors strongly depends on the volumecarrier density. In order to achieve high mobility for high performanceapplications, the volume carrier density of the metal oxide channel ishigh. Traditionally, the volume carrier concentration in metal oxide iscontrolled by oxygen vacancies. Therefore, it is essential for highmobility MOTFTs that the concentration of the oxygen vacancies in thecarrier transport layer (MOTFT channel), be as high as possible and thatthe oxygen vacancies not be reduced during processing or thereafter.

Referring to FIG. 1, several steps are illustrated in a process offabricating a high mobility stable transport structure. Initially asubstrate 12 is provided, which may be any convenient supportingmaterial and in a preferred embodiment is a material transparent to aradiation wavelength used in a self-alignment procedure, or transparentin the case of bottom emission light emitting displays or transmissiveliquid crystal displays. Typical materials for the transparent substrate12 include glass, plastic film, etc. In applications that do not requiresubstrate transparency, polished stainless-steel sheets can also beused. Substrate 12 can be in rigid, conformable, or flexible forms.Fabrication of MOTFTs on a thin flexible plastic substrate requires allprocess temperatures below its glass temperature, Tg (above whichpermanent deformation occurs so that pattern alignment among differentlayers becomes impractical). Tg in typical polymer substrates are in a160° C. (PET)-390° C. (PI) range.)

A gate metal layer 14 is deposited on the surface of substrate 12 in anywell known manner. A thin layer 16 of gate dielectric material is formedover gate metal 14 and may be any convenient material that provides thedesired dielectric constant for TFT operation. Suitable materials forthe gate dielectric layer include SiO₂, SiN, Al₂O₃, AlN, Ta₂O₅, TiO₂,ZrO, HfO, SrO, or their combinations in blend or multiple layer form. Inaddition to conventional forming methods (such as PECVD, PVD, etc.) themetal-oxide dielectric above can also be made with surface oxidationfrom the corresponding metal. Examples of surface oxidation includeheating in oxygen-rich ambient, anodization, or their combination insequence.

A carrier transport structure 18 includes a lower active transport layerd1 of semiconductor metal oxide deposited over the upper surface oflayer 16 and a protective layer d2 deposited directly on layer d1. As isexplained in more detail below, layer d2 is deposited right after layerd1 without breaking vacuum in the deposition chamber so that forpurposes of this disclosure layers d1 and d2 are considered incombination as a carrier transport structure. In addition to depositingd1 and d2 layers without a vacuum break, it is discovered that sputterdepositing the layers without oxygen presence is preferred to achievethe high carrier mobility as is described in more detail presently.

The best materials for active transport layer d1 are transparent metaloxide semiconductors such as indium-tin-oxide (ITO), indium oxide (InO),tin oxide (SnO), cadmium oxide (CdO), zinc oxide (ZnO),indium-zinc-oxide (IZO), and the like. Composite films comprisingmultiple metal-oxide compositions listed above can also be used. Controlof chemical purity and intentional chemical doping can optimize thecarrier mobility at the desired carrier concentration level. Withcarrier transport structure 18, as disclosed herein, along with theproper selection of the dielectric constant of the gate dielectricmaterial forming layer 16, a MOTFT with a carrier concentration inactive transport layer d1 as high as 5×10¹⁹ cm⁻³ can be fabricated witheffective current switching between source and drain electrodes. In thepreferred embodiment the carrier concentration in active transport layerd1 is in a range of approximately 10¹⁸ cm⁻³ to approximately 5×10¹⁹cm⁻³.

As explained above, to achieve a high mobility device, the thickness ofthe carrier transport layer should be made as small as possible. In thepresent embodiment the thickness of active transport layer d1 is in arange of less than approximately 5 nm and may conveniently be as low asapproximately 2 nm.

Factors that must be considered in the case of using very thin filmcarrier transport layers are, for example, the stability may be or iseasily compromised by the environment and by subsequent processingsteps. In order to avoid degrading processing stability and operatingstability, thin transport layer d1 has to be protected by some moreinert layer, such as protective layer d2. Here the term “inert” isdefined to mean that layer d2 has a much lower carrier mobility andcarrier concentration, or is either an insulating material or is muchcloser to an insulating material. Protective layer d2 is preferablydeposited directly on and substantially in the same deposition process(i.e. in situ or without breaking vacuum in the deposition chamber) asthin transport layer d1. By depositing layer d2 directly on layer d1,thin transport layer d1 is not exposed to ambience or processingchemicals. The best materials to use in protective layer d2 are metaloxides that are more inert than transport layer d1, such as M-Zn—O orM-In—O or their combination in which M includes at least one of Al, Ga,Ta, Ti, Si, Ge, Sn, Mo, W, Cu, Mg, V, Zr, or the like, with sufficient Mcontent to ensure a desired inert state. The M component possessesgenerally higher bonding strength to oxygen that makes the protectionlayer d2 substantially more inert than the D1 layer. While the listedoxides are less conductive than thin transport layer d1, they are stillsufficiently conductive vertically to allow metal S/D contacts to bedeposited on protective layer d2 without the need for etching. In fact,it has been found that the deposition of contact metal on protectivelayer d2 will attract oxygen from protective layer d2 so that a goodohmic contact is the result even if protective layer d2 is inert becauseof some of the following process steps.

It is worth mentioning that in the case of a thin d1 layer (such as witha nominal thickness close to 2 nm), the bilayer structure and thecorresponding carrier transport within the bilayer structure guaranteesuniform conduction over large substrate areas even on a gate insulatorwith a relatively rough surface.

It will be understood that in the preferred fabrication process thinamorphous transport layer d1 is deposited by sputtering at lowtemperatures, preferably room temperature but no more than 160° C. Suchlow temperature process enables the TFT disclosed in this invention tobe made on plastic substrates (such as PET, PEN, PAN, PAS, PI, etc). Inorder to maximize the mobility, the residual carrier concentration inthe thin transport layer d1 should be as high as possible. To aid inachieving this result, in a preferred deposition of thin transport layerd1 no oxygen is introduced in the sputtering process. In a sputteringprocess incorporating oxygen, the oxygen is negative charged by thedeposition system and accelerated toward the substrate. In the priorart, when making metal-oxide based TFTs, artisans introduced oxygenduring sputter deposition to reduce carrier concentration to below 10¹⁷cm³ and move the threshold voltage of the MOTFT toward a more positivedirection, the accelerated oxygen ions damage the forming film andresult in defects and metastable states in the film. All the factorsproduced by the introduction of oxygen in the sputtering processcontribute to low carrier mobility and positive bias stress instability,which have been observed generally in the field.

In the prior art, it has also been known that many of the materialsdisclosed herein for the d1 layer were classically used for transparentconducting electrodes with thicknesses typically over 100 nm. Substrateheating is often used to optimize the conductivity. It is known thatultra-thin films less than 10 nm deposited under such conditions witheven the same material composition typically results in low carrierconcentration and low mobility.

In contrast, the oxygen-free sputter process disclosed in the presentinvention enables one to achieve the needed carrier concentration andhigh mobility with a nominal thickness for transport layer d1 thinnerthan 5 nm.

In the preferred embodiment and without breaking the vacuum in thesputter chamber, the inert metal oxide of protective layer d2 isdeposited by sputtering directly on layer d1 at low temperatures,preferably room temperature, but no more than 160° C. Protective layerd2 is formed with a thickness in a range of up to approximately 20 nm orgreater. In the step of depositing the inert metal oxide by sputteringthe same problems are prevalent as discussed above for active layer d1.If oxygen is introduced into the sputtering gas, the negatively chargedoxygen will be accelerated toward the substrate. Some of the acceleratedoxygen may penetrate into active transport layer d1 and createmetastable oxygen in active transport layer d1, resulting in mobilityand stability degradation. Therefore, in the preferred process the inertmetal oxide of protective layer d2 is deposited by sputtering withoutoxygen.

One possible problem that may arise from sputtering without oxygen isthat protective layer d2 may become too conductive and move thethreshold voltage of the MOTFT too negative. By annealing the structurein an oxidizing ambience at an elevated temperature (e.g. >160° C.)protective layer d2 can be oxidized to move the threshold toward thepositive direction. The problem with annealing in ambient atmosphere isthat the process will generally be too slow, especially for temperaturesbelow 200° C. Therefore, the desired oxidized result is achieved in atwo step process that is very effective at low temperatures (i.e. <160°C.)

In a first step of the oxidizing process, the surface of the inert metaloxide of protective layer d2 is treated by a chemically oxidizingprocess. In the second step, the surface oxygen is driven intoprotective layer d2 at an elevated temperature. It has been confirmedthat by driving oxygen into protective layer d1 a MOTFT with a switchthreshold voltage larger than 0V can be achieved at a temperature at orbelow approximately 160° C.

The forming of an oxygen source at the top surface of the metal oxide ofprotective layer d2 can include any one of a variety of possibleoptions. The surface oxidizing can include, for example, the use of ahigh pressure (>100 mtorr) oxygen plasma that would not include any highenergy ions that can generate a metastable state. Another oxidizingoption is the use of a high pressure (>100 mtorr) N₂O plasma. Anotheroxidizing option is the use of ultraviolet ozone. Yet another option isthe coating of protective layer d2 with a self-assembled monolayer suchas 4-chlorophenyl trichlorosilane (4-CPTS), chloromethyl trichlorosilane(CMTS), 4-chlorophenyl phosphonic acid (4-CPPA), 3-nitrophenylphosphonic acid (3-NPPA), and 2-chloroethyl phosphonic acid (2-CEPA).Yet another option is the treating of the surface of protective layer d2with concentrated hydrogen peroxide. Yet another option is the treatingof the surface of protective layer d2 with a dichromate solution.

In any of the above oxygen treatment examples or others that may bedevised, the purpose of the surface modification is to deposit aconcentrated oxygen source/reservoir on the surface of protective layerd2 which is much more concentrated than the oxygen in the ambience. Suchdeposition process is done at low temperature, for example at roomtemperature without intentional substrate heating. Oxygen diffusionduring this process is negligible. The concentrated oxygen source on thesurface of protective layer d2 is then subjected to an elevatedtemperature (e.g. at ˜160° C., or higher) which causes the oxygen tomigrate into protective layer d2. The migration of oxygen intoprotective layer d2 makes the inert metal oxide more oxidized and movesthe threshold voltage closer to zero. Since the process of driving thesurface oxygen into protective layer d2 is thermally activated, theoxygen will stay in protective layer d2 because the composition of theinert metal oxide selected for protective layer d2 is more stable thanthe material forming active transport layer d1. The oxidizing processfor protective layer d2 enables a lower elevated temperature stepbecause of the very concentrated source of oxygen at the surface (i.e.the oxygen diffusion is concentration dependent).

The process above provides a method to make a high mobility, amorphousbi-layer on plastic substrates (such as PET, PEN, PAN, PAS, and PI). Themaximum temperature of ˜160° C. fits with PET substrates. For PEN, PAN,and PAS, the temperature for the diffusion process can be increased to a180-220° C. range. For the case of a PI (polyimide) substrate orflexible glass substrate (such as Corning Willow glass series), highertreatment temperature can be chosen to reduce the process times. For thecase with a borosilicate glass substrate, the treatment temperature canbe selected in an even broader range. On the other hand, to retain thetransport layer amorphous (i.e. with no crystal grain larger than 100nm), the oxygen diffusion process is preferred to be carried out below350° C.

It is worth noting that the greater tendency of oxidation in protectivelayer d2 with respect to transport layer d1 reduces carrier density andmobility in protective layer d2 and also depletes oxygen from transportlayer d1 to improve the carrier concentration and mobility in transportlayer d1. As a result, the field effect mobility in MOTFTs fabricated inaccordance with the process disclosed in the present invention issubstantially higher than was realized in the prior art devices in whichthick transport oxide films were used for electrodes. For instance, amobility over 90 cm²/Vsec has been achieved in MOTFTs in which transportlayer d1 is made of thin, amorphous In—Sn—O film (In2O3:SnO, weightratio equals 90:10), in contrast to a 30-50 cm²/Vsec observed in thickcrystalline conducting electrode films with similar In—Sn—O composition.

Turning specifically to FIG. 2, a high mobility stable, amorphous MOTFT10, of the “etch-stop” MOTFT type, is illustrated. For purposes of thisdisclosure, MOTFT 10 is defined as an “etch-stop” MOTFT. A completeprocess for this fabrication technique can be found in a copending U.S.patent application entitled “Double Self-Aligned Metal Oxide TFT”, filedMay 26, 2011, bearing Ser. No. 13/116,292, and incorporated herein byreference. MOTFT 10 includes transparent substrate 12, which may be anyconvenient material transparent to radiation (i.e. self-alignmentexposure) wavelengths used in the self-alignment procedure, such asglass, plastic, etc. For the MOTFT to be used for opto-electric orelectro-optic applications, transparency to wavelengths being used isalso needed. For example, transparency in the visible range (400-700 nm)is required for display applications, or transparency from 200 nm-3200nm is required for broadband image sensors. Gate metal layer 14 ispatterned on the upper surface of substrate 12 by any convenient means.Since the position of gate metal layer is not critical virtually anynon-critical patterning technique can be used.

It will be understood by those of skill in the art that in addition toor instead of forming gate metal layer with a physical vapor depositionprocess (such as sputter, a-beam, thermal deposition, etc.) andpatterned by photolithography with a proximity or a projection tool, thegate layer can be formed with any of the various printing processesknown to experts in the field, including ink jetting, dispensing,imprinting, transfer printing or off-set printing methods. The gatemetal can also be formed with a plating method known in the art. Inaddition to or instead of using traditional photolithography layer 14can also be patterned with laser writing lithography. While a singlegate metal 14 (i.e. single MOTFT) is illustrated for convenience inunderstanding, it will be understood that this might represent one ormore (even all) of the TFTs used in a backplane or other large areaapplications.

Thin layer 16 of gate dielectric material is formed over gate metal 14and the surrounding area. For purposes of this disclosure the term“surrounding area” includes at least the area illustrated in FIG. 2(i.e. the gate and channel areas and the source/drain areas). Again,layer 16 may be a blanket layer covering the entire large areaapplication and no alignment is required. The gate dielectric materialmay be any convenient material that provides the desired dielectricconstant for TFT operation. Typical inorganic materials include SiO₂,SiN, Al₂O₃, Ta₂O₅, TiO₂, HfO₂, ZrO₂, SrO and the like. Organicdielectrics can also be used for layer 16. For example, a metal-oxideTFT with organic gate dielectric is disclosed in U.S. Pat. No.7,772,589. In addition to single compounds, gate dielectric layer 16 canbe constructed with these materials in mixed composite form, or in amultiple-layer stack.

Carrier transport structure 18, including the amorphous semiconductormetal oxide bilayer di/d2, is deposited over the upper surface of layer16. As mentioned earlier, typical materials for active transport layerd1 are transparent metal oxide semiconductors such as indium-tin-oxide(ITO), indium oxide (InO), tin oxide (SnO), cadmium oxide (CdO), zincoxide (ZnO), indium-zinc-oxide (IZO), and the like. Composite filmscomprising multiple metal-oxide components listed above can also beused. A desired carrier concentration can be achieved by chemical dopingand by the bilayer d1/d2 structure deposited by a sputter processsequentially in an oxygen-free environment and without substrateheating. It should be noted that, although the completed d2 layer ismore inert chemically and more resistive electrically, the pristinedeposited d2 layer in an oxygen-free environment is selected (throughthe proper selection of the metal components) to have a higher tendencyto attract oxygen from both the top surface and the bottom surfacecontacting layer d1. Attracting oxygen from active transport layer d1results in optimized carrier concentration and carrier mobility inactive transport layer d1.

Carrier transport structure 18 can then be patterned with standardphotolithography and a surface oxidation process is performed followedwith an oxygen diffusion process at an elevated temperature. Theresulting structure 18 is amorphous/nanocrystalline without crystallinestructure beyond 100 nm.

A passivation/etch-stop layer 20 is then deposited on carrier transportstructure 18 and patterned. In addition to or instead of inorganicmaterials (such as Al₂O₃, Ta₂O₅, TiO₂, SiN, and SiO₂), aphoto-patternable organic material can also be used for the layer 20.The selection principle for layer 20 is that the material and thecorresponding forming process do not create damage in the underlyingcarrier transport structure 18. U.S. Pat. Nos. 7,977,151 and 8,187,929and U.S. patent application Ser. Nos. 13/115,749 and 13/718,813,incorporated herein by reference, disclose a series of such materialsand processes.

Layer 20 is used as an etch stop/passivation layer during the followingprocesses. The patterning can be accomplished with regularphotolithography or by a self-aligned process using the gate pattern asa built-in mask. Details on the self-aligned process are disclosed inU.S. Pat. Nos. 7,605,026 and 7,977,151.

The source/drain areas 22 can be formed by physical vapor deposition andby standard etching methods known to artisans in the field. Areas 22 canalternatively be formed with self-aligned process by means of gate layerpattern and a non-crucial lithography mask, or by means of anadd-on/printing method (such as plating) as disclosed in U.S. Pat. No.7,977,151 and U.S. patent application Ser. No. 13/406,824. The spacebetween the source and drain, i.e. etch stop/passivation layer 20,defines the conduction channel, designated 24, for MOTFT 10.

Optional cleaning/treatment/etching processes (with plasma or chemicaltreating) could be inserted after the processing of etchstop/passivation layer 20 and before deposition of source/drain areas 22to improve the electrical contact between carrier transport structure 18and S/D electrodes (source/drain areas 22). Etch stop/passivation layer20 provides the needed protection to the channel area during theseprocesses.

Turning to FIG. 3, another metal oxide thin film transistor (MOTFT) 30is illustrated in accordance with the present invention. In thisexample, MOTFT 30 includes a substrate 34 with a bottom gate 36 formedthereon and a gate dielectric layer 38 overlying gate 36. An activelayer 40 of metal oxide is formed on gate dielectric layer 38 andsource/drain metal contacts 42 are positioned in a spaced apartrelationship on active layer 40 to define a channel area therebetween ina well known manner. Active layer 40 is a carrier transport structureconstructed similar to carrier transport structure 18 of FIG. 1 andincludes a lower active transport layer d1 of high mobility amorphoussemiconductor metal oxide deposited over the upper surface of layer 38and a protective layer d2 deposited directly on layer d1. This type ofMOTFT is known as a ‘back-channel etch’ MOTFT and illustrates that astable high mobility amorphous MOTFT can also be fabricated using theback-channel-etching process.

Gate 36 and layers 38 and 40 are formed on substrate as described abovewith respect to FIGS. 1 and 2. Source/drain metal contacts 42 arepreferably formed by first depositing a blanket layer of contact metal.After blanket depositing the S/D metal layer, the layer is patterned byeither a dry or wet etchant to open the channel area, designated 44. Thesurface of channel area 44 can be cleaned by a washing procedure andfollowed with a surface treatment procedure. In ‘back-channel etch’MOTFT 30 configuration, channel area 44 is available for the step orsteps of oxidation and oxygen drive-in after the S/D patterning and ispreferred at this point in the fabrication process. The greater tendencyof oxidation in protective layer d2 with respect to transport layer d1protects layer d1 during the S/D deposition and patterning process andthe subsequent step or steps of oxidation and oxygen drive-in ensuresthe desired carrier concentration and mobility in channel area 44.

For certain applications, such as the configuration of FIG. 3,additional organic/inorganic passivation layer(s) and electrode layersmay be needed subsequent to the formation and patterning of the S/Dlayer. Due to the improved chemical resistance disclosed in thisinvention, a larger process window, more process methods, and broadermaterial selection can be used for the following processes.

Referring to FIGS. 4A and 4B, two typical Id-Vgs data sets areillustrated from MOTFTs fabricated in accordance with the presentinvention. Referring specifically to FIG. 4A, a data set is illustratedfrom a TFT with etch-stop structure as described in conjunction withFIG. 2. Referring specifically to FIG. 4B, a data set is illustratedfrom a TFT with BCE structure as described in conjunction with FIG. 3.The Id-Vgs data were taken at Vds=1V and 10V at room temperature. Thecorresponding linear mobility and saturate mobility are also shown atthe right side of each FIG. The gate metal for these TFTs was an Al—Ndalloy. The gate insulator was formed by surface anodization at roomtemperature. The transport layer was ITO with an In:Sn ratio of 90:10.The thickness of layer d1 was 2.5 nm. Protection layer d2 was In—Al—Zn—Owith a thickness of 30 nm. Layers d1 and d2 were deposited by sputteringwithout oxygen at room temperature. An oxygen source zone was formed atthe surface of layer d2 by means of oxygen plasma as disclosed above. Aprocess of driving the oxygen into layer d2 from the oxygen source zonewas carried out at 300° C. for 30 minutes. A photopatternable polyimidewas used as the passivation/etch-stop layer 20 in FIG. 2. For the TFTwith BCE structure, the oxygen surface forming and driving-in processeswere carried out after S/D deposition and patterning.

The current switch voltage is close to 0V. Sub-threshold voltage swingis −0.1V, as good as that in high-end LTPS-TFT. The Ion/Ioff ratioreaches 10¹⁰ at Vgs=+/−10V. For the TFT with etch-stop structure (FIG.4A), linear mobility reaches 62 cm²/Vsec at Vgs=12V, and saturationmobility reaches 58 cm²/Vsec at Vgs=8V. For the TFT with BCE structure(FIG. 4B), linear mobility reaches 82 cm²/Vsec at Vgs=6V, and saturationmobility reaches 97 cm²/Vsec at Vgs=3V-4V.

These data sets represent one of the best performance ever seen in thinfilm devices. The ON current in forward bias reaches a level only seenin poly-Si TFTs, or Poly-CdTe TFTs. The OFF currents in reverse bias, onthe other hand, are substantially better than in Poly-Si TFTs. Thesedata sets are as good as the best numbers seen in amorphous silicondevices. The data illustrated in FIGS. 4A and 4B, in fact, arecomparable to those only seen in MOSFET devices made on crystallinesemiconductor wafers.

Moreover, TFTs made with the fabrication methods disclosed in thisinvention show superb stability. The Vth shift under DC forward biasstress tested at Vgs=+20V, Vds+0.1V at 60° C., for 2 hours was less than0.7V, and the Vth shift under DC negative biasing stress at Vgs=−20V,Vds+0.1V at 60° C. for 2 hours was −0.3V. Current stress at 300 μAinitial current (under Vgs=Vds=5V) at 60° C. over 60 hours revealed astable operation lifetime: Vth only shifted less than 0.5V over theentire test. The total charge passing through the TFT was over 70Coulombs. Such performance enables high frame rates and pixel density inactive matrix displays both AMLCD and AMOLED/AMLED. For LCDapplications, TFT stability under backlight illumination also needs tobe considered. Such bilayer channel structure has intrinsic stabilityunder white light illumination. Experimental test results under abacklight unit with light intensity close to that in LCD TV and portabledevice applications confirmed the stability shifts less than 1V after 2hours of testing.

The mobility beyond 40 cm²/Vsec, enables displays with 8000 columns and4000 rows with frame rates up to 480 Hz. The high bias stability andcurrent operation stability, enables pixel driver circuits in activedisplay areas and column/row drivers in peripheral areas.

Such high mobility and stability MOTFT can also be used for thin filmelectronics beyond display arrays. Examples include high pixel densityand high frame rate imager sensor arrays, pressure sensor arrays, touchsensor arrays, chemical sensor arrays, or biosensor arrays. The processmethod and thin film process tools for large size substrates enablesmany applications in-capable with electronic circuits based on siliconwafers.

Referring to FIG. 5, graphs of Id-Vgs and mobility-Vgs curves from aMOTFT made on a flexible PET substrate are illustrated. The MOTFT fromwhich the graphs of FIG. 5 were generated was made with BCE structure asshown in FIG. 3. All the fabrication processes including oxygendriving-in baking were carried out at temperatures below or equal to160° C. Linear mobility reaches ˜55 cm²/Vsec at Vgs=15V, and saturationmobility reaches 43 cm²/Vsec at Vgs near 10V. The biasing stability andcurrent operation stability are close to that shown in the examplesabove.

Thus, a new and improved process for fabricating a stable high mobilitymetal oxide thin film transistor (MOTFT) is disclosed. Further, the newand improved process for fabricating a stable amorphous metal oxide thinfilm transistor (MOTFT) describes the fabrication of a MOTFT withmobility at or above 40 cm²/Vs. Also, a new and improved stableamorphous high mobility metal oxide thin film transistor (MOTFT) isdisclosed. The fabrication process includes steps for depositing acarrier transport structure with a high mobility layer and a relativelyinert protective layer deposited in situ with the high mobility layer toprotect the high mobility layer from damage due to subsequent processingsteps and ambient gasses. Also, the MOTFT is fabricated at roomtemperature and no greater than 160° C. Further, in the steps ofdepositing a carrier transport structure with a high mobility layer anda relatively inert protective layer, no oxygen is present.

While the examples described include various transparent and opaquelayers for purposes of self-alignment, it will be understood that ifself-alignment is not used in the fabrication process the various layersmay be transparent or opaque depending upon the specific material usedin the formation thereof and the application of the final product. Thevarious applications require no transparency from the substrate so that,for example, flexible stainless steel foil can be used as the substratematerial. Also, the MOTFT disclosed in this invention enablesconformable or flexible electronic devices and apparatus.

Various changes and modifications to the embodiment herein chosen forpurposes of illustration will readily occur to those skilled in the art.To the extent that such modifications and variations do not depart fromthe spirit of the invention, they are intended to be included within thescope thereof which is assessed only by a fair interpretation of thefollowing claims.

Having fully described the invention in such clear and concise terms asto enable those skilled in the art to understand and practice the same,the invention claimed is:

1-27. (canceled)
 28. A stable high mobility amorphous MOTFT comprising:a substrate with a gate formed thereon and a gate dielectric layerpositioned over the gate; a carrier transport structure on the gatedielectric layer, the carrier transport structure including a layer ofamorphous high mobility metal oxide adjacent the gate dielectric and aprotective layer of relatively inert material compared to the layer ofmetal oxide, source/drain contacts on the protective layer; and whereinthe layer of amorphous high mobility metal oxide and the protectivelayer are deposited without oxygen and in situ, the protective layerbeing relatively inert compared to the layer of amorphous high mobilitymetal oxide, the carrier transport layer and the protective layer arefurther treated by forming an oxygen-rich zone at the upper surface ofthe protective layer at a temperature below 160° C., and driving oxygeninto the protective layer from the oxygen-rich zone at an elevatedtemperature.
 29. The stable high mobility amorphous MOTFT as claimed inclaim 28 wherein the layer of amorphous high mobility metal oxideincludes a carrier concentration in a range of approximately 10¹⁸ cm⁻³to approximately 5×10¹⁹ cm⁻³.
 30. The stable high mobility amorphousMOTFT as claimed in claim 28 wherein the layer of amorphous highmobility metal oxide includes one of indium-tin-oxide (ITO), indiumoxide (InO), tin oxide (SnO), cadmium oxide (CdO), zinc oxide (ZnO),indium-zinc-oxide (IZO), or a composite film comprising combinationsthereof.
 31. The stable high mobility amorphous MOTFT as claimed inclaim 28 wherein the layer of amorphous high mobility metal oxide has athickness in a range of equal to or less than approximately 5 nm andpreferably approximately 2 nm.
 32. The stable high mobility amorphousMOTFT as claimed in claim 28 wherein the protective layer includes ametal oxide that is more inert than the amorphous high mobility metaloxide layer.
 33. The stable high mobility amorphous MOTFT as claimed inclaim 32 wherein the more inert metal oxide includes one of M-Zn—O,M-In—O, or combinations thereof, where M includes at least one of Al,Ga, Ta, Ti, Si, Ge, Sn, Mo, W, Cu, Mg, V, or Zr.
 34. The stable highmobility amorphous MOTFT as claimed in claim 28 wherein the protectivelayer includes a layer with a thickness in a range of 20 nm-50 nm. 35.The stable high mobility amorphous MOTFT as claimed in claim 28 whereinthe MOTFT is included in a thin film electric circuit.
 36. The stablehigh mobility amorphous MOTFT as claimed in claim 35 wherein the thinfilm electric circuit is included in an electronic device including oneof a display array device, an imager sensor array device, a pressuresensor array device, a touch sensor array device, a chemical sensorarray device, or a biosensor array device.
 37. The stable high mobilityamorphous MOTFT as claimed in claim 36 wherein the thin film electriccircuit is included in a pixel driver or a readout circuit inside thearray or a column/row driver circuit in a peripheral area of the array.38. A stable high mobility amorphous MOTFT comprising: a substrate witha gate formed thereon and a gate dielectric layer positioned over thegate; a carrier transport structure sputtered on the gate dielectriclayer, the carrier transport structure including a layer of amorphoushigh mobility metal oxide adjacent the gate dielectric with a thicknessin a range of equal to or less than approximately 5 nm and preferablyapproximately 2 nm, a protective layer of relatively inert materialdeposited on the layer of amorphous high mobility metal oxide with athickness in a range of 20 nm-50 nm, and the layer of amorphous metaloxide having a mobility above 40 cm²/Vs and a carrier concentration in arange of approximately 10¹⁸ cm⁻³ to approximately 5×10¹⁹ cm⁻³; andsource/drain contacts positioned on and in electrical contact with theprotective layer.
 39. The stable high mobility amorphous MOTFT asclaimed in claim 28 wherein the carrier mobility is 15 cm²/Vsec orabove.
 40. The stable high mobility amorphous MOTFT as claimed in claim28 wherein the carrier mobility is 40 cm²/Vsec or above.
 41. The stablehigh mobility amorphous MOTFT as claimed in claim 28 wherein thesubstrate includes one of glass, plastic film, and stainless steel filmeach in one of rigid, conformable, or flexible form.
 42. The stable highmobility amorphous MOTFT as claimed in claim 28 wherein the gatedielectric layer includes a layer of SiO₂, SiN, Al₂O₃, AlN, Ta₂O₅, TiO₂,ZrO, HfO, SrO, or their combinations in blend or multiple layer form.43. The stable high mobility amorphous MOTFT as claimed in claim 28further comprises a passivation/etch-stop layer over the protectionlayer and between the source and drain electrodes.
 44. The stable highmobility amorphous MOTFT as claimed in claim 43 wherein thepassivation/etch-stop layer includes a layer of Al₂O₃, Ta₂O₅, TiO₂, SiN,SiO₂, photo-patternable organic dielectric or their combinations inblend or multiple layer form.
 45. A method of fabricating a stable highmobility amorphous MOTFT comprising the steps of: providing a substratewith a gate formed thereon and a gate dielectric layer positioned overthe gate; depositing by sputtering a carrier transport structure on thegate dielectric layer without intentional substrate heating or withintentional cooling, the carrier transport structure including a layerof amorphous high mobility metal oxide adjacent the gate dielectric anda protective layer of material deposited on the layer of amorphous highmobility metal oxide both deposited without oxygen and in situ, theprotective layer being relatively inert compared to the layer ofamorphous high mobility metal oxide; forming an oxygen-rich zone at theupper surface of the protective layer at a temperature below 160° C.;and driving oxygen into the protective layer from the oxygen-rich zoneat an elevated temperature.
 46. The method as claimed in claim 45further including the steps of: defining a channel area overlying thegate in the layer of amorphous high mobility metal oxide; forming anetch-stop layer overlying the channel area subsequent to the drivingoxygen step; defining source/drain contact areas on opposed sides of thechannel area; performing a cleaning and/or treatment and/or etching stepon the surface of the source/drain contact areas; and depositing andpatterning source/drain contacts on the protective layer in thesource/drain contact areas.
 47. The method as claimed in claim 45further including, prior to the step of forming an oxygen-rich zone, thesteps of: defining a channel area overlying the gate in the layer ofamorphous high mobility metal oxide; defining source/drain contact areason opposed sides of the channel area; depositing a blanket metal layeron the protective layer; and patterning the blanket metal layer to formsource/drain electrodes in the source/drain areas and to open an areabetween the source/drain electrodes overlying the channel area.
 48. Themethod as claimed in claim 45 wherein the step of depositing a layer ofamorphous high mobility metal oxide includes depositing a layer ofamorphous metal oxide with a mobility above 15 cm²/Vs.
 49. The method asclaimed in claim 45 wherein the step of depositing a layer of amorphoushigh mobility metal oxide includes depositing a layer of amorphous metaloxide with a mobility above 40 cm²/Vs.
 50. The method as claimed inclaim 45 wherein the step of depositing a layer of amorphous highmobility metal oxide includes depositing a layer of amorphous metaloxide with a carrier concentration in a range of approximately 10¹⁸ cm⁻³to approximately 5×10¹⁹ cm⁻³.
 51. The method as claimed in claim 45wherein the step of depositing the layer of amorphous high mobilitymetal oxide includes depositing one of indium-tin-oxide (ITO), indiumoxide (InO), tin oxide (SnO), cadmium oxide (CdO), zinc oxide (ZnO)indium-zinc-oxide (IZO), or zinc oxide (ZnO), or a composite filmincluding more than one of the above metal-oxides.
 52. The method asclaimed in claim 45 wherein the step of depositing the layer ofamorphous high mobility metal oxide includes depositing a layer with athickness in a range of equal to or less than approximately 5 nm. 53.The method as claimed in claim 45 wherein the step of depositing theprotective layer includes depositing a layer with a thickness in a rangeof 20 nm-50 nm.
 54. The method as claimed in claim 45 wherein the stepof depositing the protective layer includes depositing a layer includingmetal oxides that are more inert than the amorphous high mobility metaloxide layer.
 55. The method as claimed in claim 54 wherein the step ofdepositing the more inert metal oxide includes depositing a layer of oneof M-Zn—O, M-In—O, or their combination, where M includes at least oneof Al, Ga, Ta, Ti, Si, Ge, Sn, Mo, W, Cu, V, or Zr.
 56. The method asclaimed in claim 45 wherein the step of forming the oxygen-rich zoneincludes using oxygen plasma, N2O plasma, a UV-ozone process, surfacetreatment with hydrogen-peroxide or a dichromate solution, or acombination process thereof.
 57. The method as claimed in claim 56wherein the step of forming the oxygen-rich zone is performed at apressure below 100 mtorr.
 58. The method as claimed in claim 45 whereinthe step of forming the oxygen-rich zone is by coating a thin surfactantlayer.
 59. The method as claimed in claim 45 wherein the step of drivingoxygen from the oxygen source into the protective layer includes usingan elevated temperature equal to or greater than 160° C.
 60. The methodas claimed in claim 45 wherein the step of providing the substrateincludes providing a substrate including one of glass, plastic film, andstainless steel film each in one of rigid, conformable, or flexibleform.
 61. The method as claimed in claim 45 wherein the step ofproviding the gate dielectric layer includes providing a layer includingSiO2, SiN, Al2O3, AlN, Ta₂O₅, TiO₂, ZrO, HfO, SrO, or their combinationsin blend or multiple layer form.
 62. The method as claimed in claim 61wherein the step of providing the gate dielectric layer includes formingthe gate dielectric layer by anodization, by heating under oxygen-richambient, or combinations thereof in sequence from the correspondingmetal.
 63. The method as claimed in claim 46 wherein the step of formingan etch-stop layer Al₂O₃, Ta₂O₅, TiO₂, SiN, SiO₂, photo-patternableorganic dielectric or their combinations in blend or multiple layerform.